Embodiments of the inventive concept of the present disclosure relate to an image sensor, and more particularly, to a stacked complementary metal oxide semiconductor (CMOS) image sensor having a structure in which at least two semiconductor chips are combined.
In general, a CMOS image sensor (CIS) may include a pixel area and a logic area. In the pixel area, a plurality of pixels may be arranged in a two-dimensional array structure, and each of unit pixels constituting the pixels may include one photodiode and a plurality of pixel transistors. The pixel transistors may include, for example, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor. In the logic area, logic elements for processing pixel signals from the pixel area may be arranged. A CIS may have a structure in which a pixel area and a logic area are formed in respective chips and the two chips, i.e., the respective chips, may be stacked in some examples. A CIS having a stacked structure may provide high image quality through maximization of the number of pixels in the pixel area and may contribute to optimization of the performance of logic elements in the logic area.